Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays

ABSTRACT

At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119(a) to KoreanPatent Application No. 10-2010-0080964, filed on Aug. 20, 2010, in theKorean Intellectual Patent Office (KIPO), the entire contents of whichis incorporated herein by reference.

BACKGROUND

Example embodiments relate to address scheduling methods forthree-dimensional (3D) memory cell arrays, and more particularly, toaddress scheduling methods for 3D memory cell arrays in non-volatilememory devices including a plurality of multi-level cells.

Flash memory used as electrically erasable programmable read-only memory(EEPROM) may have an advantage of random access memory (RAM) in whichdata can be readily programmed and erased and an advantage of ROM inwhich data can be retained without supply of power.

Flash memory is usually divided into NAND flash memory and NOR flashmemory. NOR flash memory may have a structure in which memory cells areindependently connected to a bit line and a word line, thereby having anexcellent random access time characteristic. On the other hand, NANDflash memory may be improved in terms of the degree of integrationbecause of its structure in which a plurality of memory cells may beconnected to one another, thereby requiring only one contact per cellstring. Accordingly, the NAND structure is usually used in highlyintegrated flash memory.

Multi-bit cells which may be capable of storing plural data in a singlememory cell. This type of a memory cell is generally called amulti-level cell (MLC). On the other hand, a memory cell capable ofstoring a single bit is called a single level cell (SLC).

There may occur a coupling effect between memory cells connected toadjacent word lines when a program operation is performed according toconventional address scheduling methods. To compensate for the couplingeffect, a program bias voltage may be applied to two adjacent word linesalternately when a 2-bit MLC is programmed. These address schedulingmethods, however, may deteriorate device operating speed.

SUMMARY

At least one example embodiment of the inventive concepts may provideaddress scheduling methods for increasing the operating performance ofthree-dimensional (3D) memory cell arrays.

According to at least one example embodiments of the inventive concepts,there is provided an address scheduling method for a non-volatile memorydevice with a 3D memory cell array including a plurality of multi-levelcells each capable of storing N bits where N is 2 or a natural numbergreater than 2. The address scheduling method includes the operations of(a) selecting a first bit line, (b) selecting a first string connectedto the first bit line, (c) performing address scheduling on N pages ofeach of multi-level cells in the first string sequentially from a bottomword line to a top word line, and (d) after completing the addressscheduling on all word lines in the first string, performing addressscheduling on second to k-th strings sequentially in the same manner asthe operation (c) where “k” is 2 or a natural number greater than 2.

The address scheduling method may further include selecting another bitline after completing the address scheduling on all pages of a pluralityof multi-level cells connected to the first bit line and performing theoperations (b) through (d).

According to other example embodiments of the inventive concepts, thereis provided an address scheduling method for a non-volatile memorydevice with a 3D memory cell array including a plurality of multi-levelcells each capable of storing N bits where N is 2 or a natural numbergreater than 2. The address scheduling method includes the operations of(a) selecting a first bit line, (b) performing address scheduling on Npages of each of the multi-level cells in a bottom word linesequentially from first to k-th strings connected to the first bit linewhere “k” is 2 or a natural number greater than 2, and (c) aftercompleting the address scheduling on the bottom word line, performingaddress scheduling on a second word line adjacent to the bottom wordline to a top word line sequentially in the same manner as the operation(b).

According to further example embodiments of the inventive concepts,there is provided a 3D non-volatile memory device including a memorycell array which includes a plurality of multi-level cells each capableof storing N bits where N is 2 or a natural number greater than 2 and acontrol circuit configured to control address scheduling of the memorycell array.

The control circuit may control another bit line to be selected and theabove-described operations (b) through (d) to be performed after theaddress scheduling on all pages of a plurality of multi-level cellsconnected to the first bit line is completed.

According to other example embodiments, a memory system includes theabove-described 3D non-volatile memory device and a memory controllerconfigured to control the 3D non-volatile memory device. The memorysystem may be a solid state drive (SSD).

According to yet other example embodiments, a data storage apparatusincludes a plurality of memory modules forming a redundant array ofindependent disks (RAID) array, each of which includes a plurality of 3Dnon-volatile memory devices and a memory controller configured tocontrol the operation of the 3D non-volatile memory devices; and a RAIDcontroller configured to control the operation of the memory modules.

According to at least one example embodiment, an address schedulingmethod includes selecting a first bit line connected to first throughkth strings of multi-level cells, where “k” is a natural number greaterthan or equal to 2, selecting and deselecting each of the stringssequentially from the first string to the kth string and performingaddress scheduling on N pages of each multi-level cell in each of theselected strings sequentially from a bottom word line to a top wordline, where N is a natural number.

According to at least one example embodiment, an address schedulingmethod includes selecting a first bit line connected to first throughkth strings of multi-level cells, where “k” is a natural number greaterthan or equal to 2, selecting and deselecting each of first word linessequentially from a first bottom word line to a first top word line, andperforming address scheduling on N pages of each multi-level cellconnected to each of the selected first word lines sequentially from thefirst to kth string, where N is a natural number.

According to at least one example embodiment, a non-volatile memorydevice with a three-dimensional (3D) memory cell array includes a memorycell array including a plurality of multi-level cells each configured tostore N bits, where N is a natural number greater than or equal to 2 anda control circuit configured to control address scheduling of the memorycell array, including selecting a first bit line of the memory cellarray, the first bit line connected to first through kth strings ofmulti-level cells, where “k” is a natural number greater than or equalto 2, selecting and deselecting each of the strings sequentially fromthe first string to the kth string, and performing address scheduling onN pages of each multi-level cell in each of the selected stringssequentially from a bottom word line to a top word line.

According to at least one example embodiment, a non-volatile memorydevice with a three-dimensional (3D) memory cell array includes a memorycell array including a plurality of multi-level cells each configured tostore N bits, where N is a natural number greater than or equal to 2 anda control circuit configured to control address scheduling of the memorycell array, including selecting a first bit line of the memory cellarray, the first bit line connected to first through kth strings ofmulti-level cells, where “k” is a natural number greater than or equalto 2, selecting and deselecting each of first word lines sequentiallyfrom a first bottom word line to a first top word line, and performingaddress scheduling on N pages of each multi-level cell connected to eachof the selected first word lines sequentially from the first to kthstring.

According to at least one example embodiment, a data storage apparatusincludes a plurality of memory modules in a redundant array ofindependent disks (RAID), each of the memory modules including aplurality of three-dimensional (3D) non-volatile memory devices and amemory controller configured to control the operation of the 3Dnon-volatile memory devices, each of the 3D non-volatile memory devicesincluding a memory cell array including a plurality of multi-level cellsconfigured to store N bits, where N a natural number greater than orequal to 2, and a control circuit configured to control addressscheduling of the memory cell array, the control circuit configured toselect a first bit line of the memory cell array, the first bit lineconnected to first through kth strings of multi-level cells, where “k”is a natural number greater than or equal to 2, select and deselect eachof first word lines sequentially from a first bottom word line to afirst top word line, and perform address scheduling on N pages of eachmulti-level cell connected to each of the selected first word linessequentially from the first to kth string, and a RAID controllerconfigured to control the operation of the memory modules.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the inventive concepts will be more clearlyunderstood from the following brief description taken in conjunctionwith the accompanying drawings. FIGS. 1-11 represent non-limiting,example embodiments as described herein.

FIG. 1 is a block diagram illustrating non-volatile memory systemsaccording to at least one example embodiments of the inventive concepts;

FIG. 2 is a circuit diagram illustrating a memory cell array of FIG. 1in two dimensions;

FIG. 3 is a circuit diagram illustrating a memory cell array of FIG. 1in three dimensions;

FIG. 4A is a perspective view of a non-volatile memory device accordingto at least one example embodiments of the inventive concepts;

FIG. 4B is a cross-sectional diagram of the non-volatile memory deviceillustrated in FIG. 4A;

FIGS. 5A and 5B are block diagrams illustrating address schedulingmethods for a 3D non-volatile memory device according to at least oneexample embodiments of the inventive concepts;

FIGS. 6A and 6B are flowcharts of the address scheduling methodsillustrated in FIGS. 5A and 5B, respectively;

FIGS. 7-10 illustrate memory systems including the non-volatile memorydevice of FIG. 1 according to different example embodiments of theinventive concepts; and

FIG. 11 is a block diagram illustrating data storage apparatusesincluding the memory system of FIG. 10.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which example embodiments are shown.Example embodiments may, however, be embodied in many different formsand should not be construed as being limited to the embodiments setforth herein; rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey theconcept of example embodiments to those of ordinary skill in the art. Inthe drawings, the thicknesses of layers and regions are exaggerated forclarity. Like reference numerals in the drawings denote like elements,and thus their description will be omitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle may have rounded or curved features and/or a gradient ofimplant concentration at its edges rather than a binary change fromimplanted to non-implanted region. Likewise, a buried region formed byimplantation may result in some implantation in the region between theburied region and the surface through which the implantation takesplace. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope ofexample embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIG. 1 is a block diagram illustrating non-volatile memory systems 100according to at least one example embodiment of the inventive concepts.A non-volatile memory system 100 may include a non-volatile memorydevice 120 and a memory controller 110 controlling the non-volatilememory device 120. The non-volatile memory device 120 may be a NOR flashmemory and/or a NAND flash memory, but the example embodiments are notrestricted thereto. The non-volatile memory device 120 may include amemory cell array 230, a row decoder 240, a write driver/sense amplifier(SA) circuit 250, a control circuit 260, a voltage generator 270 and aninput/output (I/O) circuit 280.

The row decoder 240 may select one word line from among a plurality ofword lines in response to a row address, may apply a first operatingvoltage to the selected word line and may apply a second operatingvoltage to unselected word lines. For instance, the row decoder 240 mayapply the first operating voltage (e.g., a program voltage) to theselected word line and the second operating voltage (e.g., a passvoltage) to the unselected word lines in a program operation and mayapply the first operating voltage (e.g., a read reference voltage) tothe selected word line and the second operating voltage (e.g., a readvoltage) to the unselected word lines in a read operation.

The write driver/SA circuit 250 may be selectively connected to aplurality of bit lines and may write and/or program data to a selectedmemory cell and/or may read data from the selected memory cell bysensing and amplifying the data. The write driver/SA circuit 250 mayinclude a plurality of data storage units (not shown) to store data setto be programmed in the program operation and to store a data set readfrom memory cells in the read operation. Each of the data storage unitsmay be implemented by a plurality of latches. The data storage units mayalso store a data set read in a program verify operation. A switchingblock (not shown) may be between the write driver/SA circuit 250 and thememory cell array 230 to selectively connect a write driver and/or a SAto the plurality of bit lines.

The control circuit 260 may output internal control signals (not shown)for controlling operations, such as program operations, eraseoperations, and read operations, of the non-volatile memory device 120in response to an external command. The control circuit 260 may controladdress scheduling of the memory cell array 230. The address schedulingmay include scheduling an address sequence. When multi-level cells(MLCs) capable of storing two bits include two pages in the memory cellarray 230, the control circuit 260 may schedule an address sequence forthe pages of the MLCs.

The voltage generator 270 may generate voltages, such as a programvoltage, a pass voltage, and a read voltage, for the operations of thenon-volatile memory device 120. The I/O circuit 280 may interface thenon-volatile memory device 120 with the outside (e.g., the memorycontroller 110). The I/O circuit 280 may receive a command and/or datato be programmed from the outside and/or transmit a state signal and/orread data to the outside. The memory controller 110 may control overalldata exchange between a host and the non-volatile memory device 120. Forexample, the memory controller 110 may control the non-volatile memorydevice 120 to write data and/or read data in compliance with the host.

FIG. 2 is a circuit diagram illustrating a memory cell array 230 of FIG.1 in two dimensions. FIG. 3 is a circuit diagram illustrating a memorycell array 230′ as an example of a memory cell array 230 of FIG. 1 inthree dimensions. Referring to FIG. 2, the memory cell array 230 mayinclude a plurality of cell strings 20-1, 20-2, . . . , and 20-m where“m” is a natural number. Each of the cell strings 20-1 through 20-m mayinclude a plurality of non-volatile memory cells. The cell strings 20-1through 20-m may be disposed in two dimensions on one plane in thememory cell array 230, as illustrated in FIG. 2, or cell strings 20′-1through 2 k′-m may be disposed in three dimensions on different planesand/or layers in a memory cell array 230′, as illustrated in FIG. 3.

The cell string 20-1 illustrated in FIG. 2 may include a first selectiontransistor ST1 connected to a bit line BL1, a second selectiontransistor ST2 connected to ground, and a plurality of non-volatilememory cells connected in series between the first and second selectiontransistors ST1 and ST2. The cell string 20-2 may include a thirdselection transistor ST3 connected to a bit line BL2, a fourth selectiontransistor ST4 connected to the ground, and a plurality of non-volatilememory cells connected in series between the third and fourth selectiontransistors ST3 and ST4. The cell string 20-m may include a fifthselection transistor ST5 connected to a bit line BLm, a sixth selectiontransistor ST6 connected to ground, and a plurality of non-volatilememory cells connected in series between the fifth and sixth selectiontransistors ST5 and ST6.

The non-volatile memory cells included in each of the cell strings 20-1through 20-m may be implemented by electrically erasable programmableread-only memory (EEPROM) cells that can store one or more bits. Thenon-volatile memory cells may be implemented by NAND flash memory cells(e.g., single level cells (SLCs) or MLCs) which can store one or morebits. The cell strings 20-1 through 20-m may be referred to as NANDstrings. String selection lines SSL may be connected to the selectiontransistors (e.g., ST1, ST2 and ST3). A common source line CSL may beconnected to selection transistors (e.g., ST2, ST4 and ST6). Word linesWL1-WLn may be connected to the plurality of non-volatile memory cells.A page buffer PB (e.g., 71-1 through 71-m) may be connected to each bitline (e.g., BL1-BLm).

As used herein, letters representing a variable, for example a naturalnumber, are not limited by a number corresponding to a position in thealphabet. Rather, letters representing a variable herein may be anynumber extending from a sequence (e.g., for 20-1, 20-2, . . . , and20-m, “m” may be any natural number greater than 2). For example, theletters “m” and “k” representing natural numbers, as used herein, may bevariables representing any natural number. Further, combinations ofletters and numbers are not constrained to a specific range. Forexample, 2k′ of 2k′-m is not limited to ten digits and expresses avariable that may be of any magnitude. The specific labeling hereinusing variables, and variable-number combinations, is for purposes ofexplanation only and a number of cells, cell strings, cells per cellstring, layers and other features of example embodiments may differ dueto, for example, an application of example embodiments.

Referring to FIG. 3, each of a plurality of layers 21-1, 21-2, . . . ,21-k (where “k” is a natural number) may include a plurality of cellstrings. The first layer 21-1 may include a plurality of cell strings20′-1 through 20′-m, the second layer 21-2 may include a plurality ofcell strings 21′-1 through 21′-m, and the k-th layer 21-k may include aplurality of cell strings 2 k′-1 through 2 k′-m. As illustrated in FIG.3, a first cell string 20′-1 may be disposed in the first layer 21-1, asecond cell string 21′-1 may be disposed in the second layer 21-2different from the first layer 21-1, and a k-th cell string 2 k′-1 maybe disposed in the k-th layer 21-k different from the second layer 21-2so that the first through k-th cell strings 20′-1, 21′-1, and 2 k′-1 aredisposed in three dimensions.

The first cell string 20′-1 in the first layer 21-1 may include aplurality of non-volatile memory cells (e.g., NAND flash memory cells)connected in series between a plurality of selection transistors ST11and ST21. The second cell string 21′-1 in the second layer 21-2 mayinclude a plurality of non-volatile memory cells (e.g., NAND flashmemory cells) connected in series between a plurality of selectiontransistors ST12 and ST22. The k-th cell string 2 k′-1 in the k-th layer21-k may include a plurality of non-volatile memory cells (e.g., NANDflash memory cells) connected in series between a plurality of selectiontransistors ST1 k and ST2 k.

A row decoder 240′ illustrated in FIG. 3 may provide selection signals(e.g., a read voltage during a read operation, a power supply voltageduring a program operation and 0 V during an erase operation) to stringselection lines SSL1, SSL2, . . . , and SSLk connected to the gates ofthe first selection transistors ST11, ST12, . . . , and ST1 k,respectively, implemented in the layers 21-1 through 21-k, respectively.The first selection transistors ST11-ST1 k may be selectively turned onor off. The row decoder 240′ may also provide selection signals (e.g.,the read voltage during the read operation and 0 V during the programoperation and the erase operation) to ground selection lines GSL1, GSL2,. . . , and GSLk connected to the gates of the second selectiontransistors ST21, ST22, . . . , and ST2 k, respectively, implemented inthe layers 21-1 through 21-k, respectively. The second selectiontransistors ST21 through ST2 k may be selectively turned on or off. Eachof the cell strings 20′-1 through 2 k′-m implemented in the respectivelayers 21-1 through 21-k may be selected by the row decoder 240′.

As illustrated in FIG. 3, the cell strings 20′-1 through 2 k′-1 mayshare with one another a plurality of word lines WL1-WLn, a commonsource line CSL and a bit line BL1. Cell strings at correspondingpositions in the respective layers 21-1 through 21-k may be connected toa corresponding one among the page buffers 71-1 through 71-m included ina write driver/SA circuit 250′.

FIG. 4A is a perspective view of a non-volatile memory device 120according to at least one example embodiments of the inventive concepts.FIG. 4B is a cross-sectional diagram of the non-volatile memory device120 illustrated in FIG. 4A. Referring to FIGS. 4A and 4B, gateinterlayer insulating layers 136 and conductive layers GSL, WL1-WLn, andSSL may be alternately and repeatedly stacked on a semiconductorsubstrate 122. A well region 124 may be on the semiconductor substrate122 and may be a common source line CSL. The well region 124 mayinclude, for example, an n+ conductivity type region. The gateinterlayer insulating layers 136 and the conductive layers GSL, WL1-WLn,and SSL may be alternately stacked on the well region 124. Theconductive layers GSL, WL1-WLn, and SSL may be sequentially stacked inorder of GSL, WLn-WL1, and SSL. The gate interlayer insulating layers136 may include an insulating material (e.g., a silicon oxide layerand/or a silicon nitride layer).

Among the stacked conductive layers GSL, WL1-WLn, and SSL, the top andbottom layers SSL and GSL may be used as a string selection line andground selection line and the remaining conductive layers WL1-WLn may beused as word lines. The word lines WL1-WLn may include a conductivematerial (e.g., poly silicon and/or metal). A plurality of activepillars PL may pierce through the gate interlayer insulating layers 136and the conductive layers GSL, WL1-WLn, and SSL. The active pillars PLmay include, for example, a semiconductor material and may correspond tocell strings in a non-volatile memory device 120. The channels ofselection transistors and memory cell transistors in each string may beelectrically connected through the active pillars PL. The active pillarsPL may be separated from one another, and may be electrically connectedto the well region 124 on the semiconductor substrate 122 by piercingthrough the conductive layers GSL, WL1-WLn, and SSL.

The active pillars PL may protrude toward the conductive layers GSL,WL1-WLn, and SSL at each of the conductive layers GSL, WL1-WLn, and SSL.Each of the active pillars PL may include a body 132 extendingvertically from the top of the semiconductor substrate 122 and aplurality of protrusions 134 which may extend from the body 132 towardthe conductive layers GSL, WL1-WLn, and SSL and may be separated fromone another. At each of the conductive layers GSL, WL1-WLn, and SSL, aprotrusion 134 may face a corresponding one of the conductive layersGSL, WL1-WLn, and SSL, surrounding the body 132.

On the active pillars PL may be formed bit lines BL electricallyconnected to the active pillars PL. Each of the bit lines BL may crossstring selection lines SSL and may be electrically connected to activepillars PL in one row and/or column among the active pillars PL. Achannel may be formed at each of the protrusions 134 during operation ofthe non-volatile memory device 120. A charge storage layer pattern 126may be between the protrusions 134 of each active pillar PL and the sidewalls of the conductive layers GSL, WL1-WLn, and SSL. The charge storagelayer pattern 126 may contact the conductive layers GSL, WL1-WLn, andSSL and may cover the surface of the protrusions 134 and the body 132 ofeach active pillar PL. A pattern of the charge storage layer pattern 126may be a ribbed pattern and may reduce interference between cellscompared to a straight line shaped charge storage layer pattern.

When a three-dimensional (3D) non-volatile memory device is of astructure illustrated in FIGS. 4A and 4B, address scheduling methodsaccording to example embodiments may be used for the 3D non-volatilememory device. Program performance may increase.

FIGS. 5A and 5B are block diagrams illustrating address schedulingmethods for a 3D non-volatile memory device according to at least oneexample embodiments of the inventive concepts. FIGS. 5A and 5B mayillustrate string selection lines SSL1-SSLk, bit line BL1 and word linesWL1-WLn illustrated in FIG. 3. Each of the word lines WL1-WLn may beconnected to a plurality of MLCs. Each of the MLCs may include N pagesto program N bits where N may be 2 or a natural number greater than 2.For example, when each MLC may store two bits, the MLC may include twopages. Example embodiments may be explained with reference to an MLCthat may store two bits, but example embodiments of the inventiveconcepts may not be restricted thereto.

Referring to FIG. 5A, a first string selection line SSL1 connected to abit line BL1 may be selected and bottom to top word lines WL1-WLn may besequentially selected. In a program operation, after all pages (e.g.,first and second pages) of an MLC connected to the first stringselection line SSL1 at the bottom word line WL1 are programmed, allpages of an MLC connected to the first string selection line SSL1 at thenext word line WL2 adjacent to the bottom word line WL1 may beprogrammed. All pages may be sequentially programmed up to the top wordline WLn. Address scheduling of the second string selection line SSL2may be performed (e.g., after the address scheduling of the first stringselection line SSL1 may be completed) in the same manner. Addressscheduling may be performed through to the last (e.g., the k-th) stringselection line SSLk. When there may be 8 word lines WL1-WL8 and 8 stringselection lines SSL1-SSL8 with 8 strings 20′-1 to 28′-1, as shown inFIG. 5A, the address scheduling may be performed as illustrated for0-127 numbered in the arrow-headed direction illustrated in FIG. 5A.

Referring to FIG. 5B, addresses may be scheduled sequentially from thebottom word line WL1 to the top word line WLn with respect to the bitline BL1. Differently from the address scheduling method illustrated inFIG. 5A, the address scheduling illustrated in FIG. 5B may select one ofthe word lines WL1-WLn first and sequentially select the first to thek-th string selection lines SSL1-SSLk with respect to the selected wordline. For example, pages (e.g., first and second pages) of all MLCsconnected to the bottom word line WL1 may be sequentially programmedfrom the first string selection line SSL1 to the k-th string selectionline SSLk. After the address scheduling of the bottom word line WL1 maybe completed, all pages of the next word line WL2 may be programmed inthe same manner. All pages may be sequentially programmed up to the topword line WLn. When there may be 8 word lines WL1-WL8 and 8 stringselection lines SSL1-SSL8 as shown in FIG. 5B, the address schedulingmay be performed as shown for 0-127 numbered in the arrow-headeddirection illustrated in FIG. 5B.

When the address scheduling methods illustrated in FIGS. 5A and 5B areused, a program operation may be carried out by only applying a biasvoltage one time to each of word lines instead of sequentially andalternately applying the bias voltage to the word lines, and the speedof the program operation may be increased.

FIGS. 6A and 6B are flowcharts of the address scheduling methodsillustrated in FIGS. 5A and 5B, respectively. Referring to FIG. 6A, afirst bit line may be selected in operation S110. A first stringconnected to the first bit line may be selected in operation S120.Address scheduling may be performed on N pages of each MLC in the firststring sequentially from a bottom word line to a top word line inoperation S130. Address scheduling may be performed in the same manneras operation S130 with respect to second to k-th strings sequentially(e.g., after the address scheduling of the pages of all word lines inthe first string may be completed) in operation S140 where “k” may be 2or a natural number greater than 2. After address scheduling of thepages of all MLCs connected to the first bit line may be completed,another bit line may be selected and operations S120-S140 may beperformed.

Referring to FIG. 6B, a first bit line may be selected in operationS210. Address scheduling may be performed on N pages of each of the MLCsin a bottom word line sequentially from first to k-th strings connectedto the first bit line in operation S220 where “k” may be 2 or a naturalnumber greater than 2. Address scheduling may be performed from a secondword line adjacent to the bottom word line to a top word line (e.g.,after the address scheduling on the bottom word line may be completed)sequentially in the same manner as operation 5220 in operation 5230.After address scheduling of the pages of all MLCs connected to the firstbit line are completed, another bit line may be selected and operations5220 and 5230 may be performed.

FIG. 7 is a block diagram of memory systems 700 including non-volatilememory devices 120 illustrated in FIG. 1 according to at least oneexample embodiment of the inventive concepts. A memory system 700illustrated in FIG. 7 may be, for example, a flash memory card includinga non-volatile memory device 120 controlling operating time according toan operating voltage applied to a selected word line, a memorycontroller 710 and a card interface 720. The memory controller 710 maycontrol data exchange between the non-volatile memory device 120 and thecard interface 720.

A memory system 700 may be a smart card. The card interface 720 may be asecure digital (SD) card interface and/or a multi-media card (MMC)interface, but example embodiments are not limited thereto. The cardinterface 720 may control data exchange between a host HOST and thememory controller 710 according to the type of the host HOST. When amemory system 700 is connected to a host (e.g., a computer, a digitalcamera, a digital audio player, a cellular phone, a console video gamehardware, and/or a digital set-top box) the memory controller 710 of thememory system 700 and a controller included in the host HOST maytransmit and receive data stored in the non-volatile memory device 120.

FIG. 8 is a block diagram of memory systems 800 including non-volatilememory devices 120 illustrated in FIG. 1 according to other exampleembodiments of the inventive concepts. Referring to FIG. 8, a memorysystem 800 may be a flash memory apparatus and may include anon-volatile memory device 120 controlling operating time according toan operating voltage applied to a selected word line, and a memorycontroller 810 controlling the operation of the non-volatile memorydevice 120. The memory controller 810 may include a memory device 811that may be used as an operation memory for a central processing unit(CPU) 813. The memory device 811 may include dynamic random accessmemory (DRAM) and/or a static RAM (SRAM).

A host interface 815 may transfer data between a host HOST connected tothe memory system 800 and the memory controller 810 according to theprotocol of the host HOST. An error correction code (ECC) block 817 maydetect and correct errors in data read from the non-volatile memorydevice 120. A memory interface 819 may transfer data between thenon-volatile memory device 120 and the memory controller 810. The CPU813 may control data exchange among the memory device 811, the hostinterface 815, the ECC block 817, and the memory interface 819 through abus 812. The memory system 800 may be, for example, a universal serialbus (USB) flash drive and/or a memory stick.

FIG. 9 is a block diagram of memory systems 300 including non-volatilememory devices 120 illustrated in FIG. 1 according to further exampleembodiments of the inventive concepts. Referring to FIG. 9, a memorysystem 300 may be, for example, a cellular phone, a smart phone, apersonal digital assistant (PDA), a digital camera, a portable gameconsole, an MP3 player, a high-definition television (HDTV), a globalpositioning system (GPS), a navigator, consumer equipment (CE), adigital set-top box, and/or an information technology (IT) device. Thememory system 300 may include a CPU 310 and at least one non-volatilememory device 120 which may be connected to each other through a bus301. The memory system 300 may include the CPU 310 and the memory system700 and/or 800 illustrated in FIG. 7 or 8, which may be connected toeach other through the bus 301.

The CPU 310 may control the operations (e.g., program, read and eraseoperations) and/or data transmission to a host of a non-volatile memorydevice 120 and/or a memory system 700 and/or 800. A memory device 320connected to the bus 301 may be used as an operation memory for the CPU310. The memory device 320 may include DRAM and/or SRAM. The memorydevice 320 may be a memory module (e.g., a single inline memory module(SIMM) and/or a dual inline memory module (DIMM)) including a pluralityof non-volatile memory devices 120 illustrated in FIG. 1.

The memory system 300 may include a first user interface 330, forexample, a display and/or a touch pad. The memory system 300 may includea second user interface 340 such as an I/O interface. The second userinterface 340 may be an output device, or example, a printer and/or aninput device (e.g., a keyboard and/or a mouse). The first user interface330 may be replaced by, for example, a complementary metal-oxidesemiconductor (CMOS) image sensor. The CMOS image sensor may becontrolled by the CPU 310 to convert an optical image into a digitalimage and store the digital image in the non-volatile memory device 120and/or the memory system 700 and/or 800.

FIG. 10 is a block diagram of memory systems 400 including non-volatilememory devices 120 illustrated in FIG. 1 according to yet other exampleembodiments of the inventive concepts. Referring to FIG. 10, a memorysystem 400 may be or may include a solid state drive (SSD). The memorysystem 400 may include a plurality of non-volatile memory devices 120and a memory controller 410 controlling the operation of thenon-volatile memory devices 120. Each of the non-volatile memory devices120 may adaptively control operating time for determining and/orverifying whether a selected memory cell among a plurality ofnon-volatile memory cells in each non-volatile memory device 120 hasbeen programmed and/or erased in compliance with the memory controller410. The memory controller 410 may communicate with a host HOST.

FIG. 11 is a block diagram data storage apparatuses 500 including memorysystems 400 illustrated in FIG. 10. Referring to FIGS. 10 and 11, thedata storage apparatus 500 may be a redundant array of independent disks(RAID) system and include a RAID controller 510 and a plurality ofmemory modules 400-1 through 400-S where “S” is a natural number. Eachof the memory modules 400-1 through 400-S may be a memory system 400illustrated in FIG. 10. The memory modules 400-1 through 400-S may bepart of a RAID array. The data storage apparatus 500 may be or mayinclude a personal computer (PC) and/or an SSD.

A data storage apparatus 500 which may be implemented by a redundantarray of independent disks (RAID) system may include a plurality ofmemory modules and a RAID controller 510. The plurality of memorymodules may form a redundant array of independent disks (RAID) array.Each of the memory modules 400-1 through 400-S may include a pluralityof the non-volatile memory devices 120 and a memory controller 410 thatmay control the operation of the non-volatile memory devices 120. TheRAID controller 510 may control the operation of the memory modules400-1 through 400-S.

In a write and/or program operation, the RAID controller 510 may outputwrite and/or program data received from a host to one of the memorymodules 400-1 through 400-S according to one RAID level selected fromamong a plurality of RAID levels based on RAID level information inresponse to a write and/or program command received from the host HOST.In a read operation, the RAID controller 510 may output to the host dataread from one of the modules 400-1 through 400-S according to one RAIDlevel selected from among a plurality of RAID levels based on RAID levelinformation in response to a read command received from the host.

As described above, according to at least one example embodiment of theinventive concepts, address scheduling methods for a 3D memory cellarray may increase the operating performance of a memory device. Exampleembodiments of the inventive concepts may be embodied as hardware,software or combination thereof. Example embodiments of the inventiveconcepts may be embodied as computer-readable codes on acomputer-readable medium. The computer-readable recording medium may beany data storage device that can store data as a program which can bethereafter read by a computer system. Examples of the computer-readablerecording medium may include read-only memory (ROM), random-accessmemory (RAM), CD-ROMs, magnetic tapes, floppy disks, and/or optical datastorage devices. The computer-readable recording medium can also bedistributed over network coupled computer systems so that thecomputer-readable code is stored and executed in a distributed fashion.

While example embodiments have been particularly shown and described, itwill be understood by one of ordinary skill in the art that variationsin form and detail may be made therein without departing from the spiritand scope of the claims.

1. An address scheduling method, comprising: selecting a first bit lineconnected to first through k^(th) strings of multi-level cells, where“k” is a natural number greater than or equal to 2; selecting anddeselecting each of the strings sequentially from the first string tothe k^(th) string; and performing address scheduling on N pages of eachmulti-level cell in each of the selected strings sequentially from abottom word line to a top word line, where N is a natural number.
 2. Theaddress scheduling method of claim 1, wherein the first through k^(th)strings are part of a non-volatile memory device with athree-dimensional (3D) memory cell array including a plurality ofmulti-level cells each configured to store up to N bits where N is anatural number greater than or equal to
 2. 3. The address schedulingmethod of claim 2, further comprising: selecting a second bit lineconnected to first through m^(th) strings of multi-level cells after theperforming address scheduling is completed on all the pages of themulti-level cells connected to the first bit line, where “m” is anatural number greater than or equal to 2; selecting and deselectingeach of the strings connected to the second bit line sequentially fromthe first string to the m^(th) string; and performing address schedulingon N pages of each multi-level cell in each of the selected stringsconnected to the second bit line from a bottom word line to a top wordline, where N is a natural number.
 4. The address scheduling method ofclaim 2, wherein the address scheduling method is performed duringprogramming of the 3D memory cell array.
 5. The address schedulingmethod of claim 2, wherein the non-volatile memory device includes atleast one of a NAND and NOR flash memory device.
 6. An addressscheduling method, comprising: selecting a first bit line connected tofirst through k^(th) strings of multi-level cells, where “k” is anatural number greater than or equal to 2; selecting and deselectingeach of first word lines sequentially from a first bottom word line to afirst top word line; and performing address scheduling on N pages ofeach multi-level cell connected to each of the selected first word linessequentially from the first to k^(th) string, where N is a naturalnumber.
 7. The address scheduling method of claim 6, wherein the firstto k^(th) strings are part of a non-volatile memory device with athree-dimensional (3D) memory cell array including a plurality ofmulti-level cells each configured to store up to N bits where N is anatural number greater than or equal to
 2. 8. The address schedulingmethod of claim 7, further comprising: selecting a second bit lineconnected to first through m^(th) strings of multi-level cells after theperforming address scheduling is completed on all of the pages of themulti-level cells connected to the first bit line, where “m” is anatural number greater than or equal to 2; selecting and deselectingeach of second word lines sequentially from a second bottom word line toa second top word line; and performing address scheduling on N pages ofeach multi-level cell connected to each of the selected second wordlines sequentially from the first to m^(th) string, where N is a naturalnumber.
 9. (canceled)
 10. The address scheduling method of claim 7,wherein the address scheduling method is performed during programming ofthe 3D memory cell array.
 11. The address scheduling method of claim 6,wherein the non-volatile memory device is at least one of a NAND flashmemory device and a NOR flash memory device.
 12. A non-volatile memorydevice with a three-dimensional (3D) memory cell array, comprising: amemory cell array including a plurality of multi-level cells eachconfigured to store N bits, where N is a natural number greater than orequal to 2; and a control circuit configured to control addressscheduling of the memory cell array, including selecting a first bitline of the memory cell array, the first bit line connected to firstthrough k^(th) strings of multi-level cells, where “k” is a naturalnumber greater than or equal to 2, selecting and deselecting each of thestrings sequentially from the first string to the k^(th) string, andperforming address scheduling on N pages of each multi-level cell ineach of the selected strings sequentially from a bottom word line to atop word line.
 13. The non-volatile memory device of claim 12, whereinthe control circuit is configured to select a second bit line of thememory cell array after completing the address scheduling on all pagesof multi-level cells connected to the first bit line, the second bitline connected to first through m^(th) strings of multi-level cells,where “m” is a natural number greater than or equal to 2, select anddeselect each of the strings connected to the second bit linesequentially from the first string to the m^(th) string, and performaddress scheduling on N pages of each multi-level cell in each of theselected strings connected to the second bit line from a bottom wordline to a top word line.
 14. The non-volatile memory device of claim 12,wherein the control circuit is configured to perform address schedulingduring programming of the memory cell array.
 15. A non-volatile memorydevice with a three-dimensional (3D) memory cell array comprising: amemory cell array including a plurality of multi-level cells eachconfigured to store N bits, where N is a natural number greater than orequal to 2; and a control circuit configured to control addressscheduling of the memory cell array, including selecting a first bitline of the memory cell array, the first bit line connected to firstthrough k^(th) strings of multi-level cells, where “k” is a naturalnumber greater than or equal to 2, selecting and deselecting each offirst word lines sequentially from a first bottom word line to a firsttop word line, and performing address scheduling on N pages of eachmulti-level cell connected to each of the selected first word linessequentially from the first to k^(th) string.
 16. The non-volatilememory device of claim 15, wherein the control circuit is configured toselect a second bit line of the memory cell array after the performingaddress scheduling is completed on all of the pages of the multi-levelcells connected to the first bit line, the second bit line connected tofirst through m^(th) strings of multi-level cells, where “m” is anatural number greater than or equal to 2, select and deselect each ofsecond word lines sequentially from a second bottom word line to asecond top word line, and perform address scheduling on N pages of eachmulti-level cell connected to each of the selected second word linessequentially from the first to m^(th) string.
 17. The non-volatilememory device of claim 15, wherein the control circuit is configured toperform address scheduling during programming of the 3D memory cellarray.
 18. A memory system comprising: the non-volatile memory device ofclaim 12; and a memory controller configured to control the non-volatilememory device.
 19. A solid state drive (SSD) comprising the memorysystem of claim
 18. 20. A data storage apparatus comprising: a pluralityof memory modules in a redundant array of independent disks (RAID), eachof the memory modules including a plurality of three-dimensional (3D)non-volatile memory devices and a memory controller configured tocontrol the operation of the 3D non-volatile memory devices, each of the3D non-volatile memory devices including a memory cell array including aplurality of multi-level cells configured to store N bits, where N anatural number greater than or equal to 2, and a control circuitconfigured to control address scheduling of the memory cell array, thecontrol circuit configured to select a first bit line of the memory cellarray, the first bit line connected to first through k^(th) strings ofmulti-level cells, where “k” is a natural number greater than or equalto 2, select and deselect each of first word lines sequentially from afirst bottom word line to a first top word line, and perform addressscheduling on N pages of each multi-level cell connected to each of theselected first word lines sequentially from the first to k^(th) string;and a RAID controller configured to control the operation of the memorymodules.
 21. The data storage apparatus of claim 20, wherein the controlcircuit is configured to select a second bit line of the memory cellarray after the address scheduling is completed on all of the pages ofthe multi-level cells connected to the first bit line, the second bitline connected to first through m^(th) strings of multi-level cells,where “m” is a natural number greater than or equal to 2, select anddeselect each of second word lines sequentially from a second bottomword line to a second top word line, and perform address scheduling on Npages of each multi-level cell connected to each of the selected secondword lines sequentially from the first to m^(th) string.
 22. (canceled)